Mar 2021-
R&D Engineer, VCS SystemVerilog compiler team, Synopsys
Shanghai
Build reliable and efficient systems in
C/C++/Rust to enhance VCS's random test case
generation
Implement latest language features in the IEEE
SystemVerilog standard
Support customers to leverage VCS's full power
to reach their verification goal
Refactor legacy codebase using modern
technologies and best engineering practice
Daily debug to troubleshoot memory-safety issues
and locate performance bottlenecks
Research on satisfiability theory, SMT solvers
and vectorization
Education
Sep 2019- Dec 2020Master of Science in Computer Engineering, GPA
3.91/4.00
Northwestern University, Evanston IL, US
Sep 2015- Jun 2019Bachelor in Integrated Circuit Design and Integrated
System, GPA 3.91/4.00
Huazhong University of Science and Technology, Wuhan,
China